Increasingly, integrated circuits (10) are becoming more powerful, with more functionality included in an IC chip. For example, a system on chip (SOC) may integrate numerous components of a computing system into a single integrated circuit chip and may include digital, analog, mixed-signal, and often radio-frequency functions in a single chip. Similarly, a multi-chip module (MOM) is a specialized electronic package where multiple bare unpackaged integrated circuits (ICs) (e.g., bare dies), semiconductor dies or other modules are packaged in such a way as to facilitate their use as a single IC. Similar to an MOM, a system-in-a-package or system in package (SiP) encloses a number of bare unpackaged ICs in a single package or module. In some cases, in an SiP, dies may be stacked vertically, unlike a slightly less dense MOM, which may place dies horizontally alongside one another.
A SiP or MOM may perform all or most of the functions of an electronic system, may be used inside a number of electronic devices, e.g., a mobile phone, digital music player, etc., and may provide a high density module that requires less space on the motherboard of a device. An exemplary SIP or MOM may contain several chips (e.g., a specialized processor, an SOC, a DRAM, a flash memory, etc.), combined with one or more passive components (e.g., resistors and capacitors), all mounted on the same substrate. Thus, a complete functional unit can be built in the SiP or the MOM so that the SiP or the MOM may not need a relatively large number of external components to function.
FIG. 1 illustrates an IC chip 10 that includes a plurality of unpackaged integrated circuits (e.g., bare dies), semiconductor dies and/or other modules. In various embodiments, the IC chip 10 may be an SiP or an MOM. The IC chip 10 may include a SOC 18 and a die 32. The SOC 18 and the die 32 may be used for a variety of purposes based on the applicability of the IC chip 10. The IC chip 10 may also include a plurality of general purpose input/output (I/O) pins 38.
In various embodiments, the SOC 18 may include a plurality of components, as is known to those skilled in the art. For example, the SOC 18 may include a CPU 22 coupled to an internal bus 36, an internal I/O module 30 coupled to the internal bus 36, etc. The internal I/O module 30 may also be coupled to the die 32.
Although the die 32 and/or the SOC 18 may be fully tested before packaging in the IC chip 10, faults within the IC chip 10, the die 32 and/or the SOC 18 may develop during or after the packaging process. For example, thermal stress or molding pressure during the packaging process may damage one or more components within the IC chip 10. As a result, it may be necessary to test the IC chip 10 after the packaging of the IC chip 10 is complete.
There may be several challenges in testing various components of the IC chip 10 once the packaging of the IC chip 10 is complete. For example, one or more of the die 32's address, data and control signals (or any other suitable types of signals) may not be directly accessible through the I/O pins 38. Additionally, the interface between the SOC 18 and the die 32 (e.g., through the internal I/O module 30) may also not be directly accessible through the I/O pins 38. These factors may prevent any external tester (e.g., an external automated test equipment (ATE)) that is external to the IC chip 10 to apply test patterns to all components of the IC chip 10 (including the die 32) and fully test the IC chip 10. Moreover, the SOC 18 (or one or more components included in the SOC 18, e.g., a memory controller (not illustrated in FIG. 1)) may not be equipped to support advanced and complicated tests, including generation of complicated test patterns, to fully test various components of the die 32.